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<A name="Par"></A>Copyright (c) 2002-2022 Lattice Semiconductor Corporation,  All rights reserved.

Sun Mar 12 05:42:29 2023

Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -exp parPathBased=ON \
	dds_pro_impl_1_map.udb dds_pro_impl_1.udb 


<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/       Number       Worst        Timing       Worst        Timing       Run          Run
Cost [udb]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            -            0            -            0            06           Completed
* : Design saved.

Total (real) run time for 1-seed: 7 secs 

par done!

Lattice Place and Route Report for Design &quot;dds_pro_impl_1_map.udb&quot;
Sun Mar 12 05:42:29 2023


<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Radiant Software (64-bit) 2022.1.0.52.3.
Command Line: par -w -t 1 -cores 1 -exp parPathBased=ON dds_pro_impl_1_map.udb \
	dds_pro_impl_1_par.dir/5_1.udb 

Loading dds_pro_impl_1_map.udb ...
Loading device for application GENERIC from file &apos;itpa08.nph&apos; in environment: G:/ProgramData/lscc/radiantide/ispfpga.
Package Status:                     Preliminary    Version 1.5.
Performance Hardware Data Status:   Advanced       Version 1.0.



Design:  hs_dac
Family:  iCE40UP
Device:  iCE40UP5K
Package: SG48
Performance Grade:   High-Performance_1.2V
WARNING - par: No master clock for
	generated clock	create_generated_clock -name {clk_60M} -source [get_pins {u_pll_60M/lscc_pll_inst/u_PLL_B/REFERENCECLK}] -multiply_by 5 [get_pins {u_pll_60M/lscc_pll_inst/u_PLL_B/OUTCORE }] .

WARNING: Database constraint &quot;create_generated_clock -name {clk_60M} -source [get_pins u_pll_60M.lscc_pll_inst.u_PLL_B/REFERENCECLK] -multiply_by 5 [get_pins u_pll_60M.lscc_pll_inst.u_PLL_B/OUTCORE]&quot; does not have corresponding timing constraint. Please check if the resource objects of the constraint are valid carefully!
Number of Signals: 586
Number of Connections: 1318

<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>

   SLICE (est.)     118/2640          4% used
     LUT            228/5280          4% used
     REG            141/5280          2% used
   PIO               18/56           32% used
                     18/36           50% bonded
   IOLOGIC            4/56            7% used
   DSP                7/8            87% used
   I2C                0/2             0% used
   HFOSC              0/1             0% used
   LFOSC              0/1             0% used
   LEDDA_IP           0/1             0% used
   RGBA_DRV           0/1             0% used
   FILTER             0/2             0% used
   SRAM               0/4             0% used
   WARMBOOT           0/1             0% used
   SPI                0/2             0% used
   EBR                6/30           20% used
   PLL                1/1           100% used
   RGBOUTBUF          0/3             0% used
   I3C                0/2             0% used
   OPENDRAIN          0/3             0% used

Pin Constraint Summary:
   18 out of 18 pins locked (100% locked).

Finished Placer Phase 0 (HIER). CPU time: 0 secs , REAL time: 0 secs 


................
Finished Placer Phase 0 (AP).  CPU time: 0 secs , REAL time: 0 secs 

Starting Placer Phase 1. CPU time: 0 secs , REAL time: 0 secs 
..  ..
....................

Placer score = 114370.

Device SLICE utilization summary after final SLICE packing:
   SLICE            118/2640          4% used

WARNING - par: No master clock for
	generated clock	create_generated_clock -name {clk_60M} -source [get_pins {u_pll_60M/lscc_pll_inst/u_PLL_B/REFERENCECLK}] -multiply_by 5 [get_pins {u_pll_60M/lscc_pll_inst/u_PLL_B/OUTCORE }] .
Finished Placer Phase 1. CPU time: 4 secs , REAL time: 4 secs 

Starting Placer Phase 2.
.

Placer score =  122551
Finished Placer Phase 2.  CPU time: 4 secs , REAL time: 4 secs 



<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>

Global Clocks :
  PRIMARY &quot;clk_60M&quot; from OUTCORE on comp &quot;u_pll_60M.lscc_pll_inst.u_PLL_B&quot; on site &quot;PLL_R13C32&quot;, clk load = 92, ce load = 0, sr load = 0

  PRIMARY  : 1 out of 8 (12%)




I/O Usage Summary (final):
   18 out of 56 (32.1%) I/O sites used.
   18 out of 36 (50.0%) bonded I/O sites used.
   Number of I/O components: 18; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+----------------+------------+------------+------------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+----------------+------------+------------+------------+
| 0        | 2 / 14 ( 14%)  | 3.3V       |            |            |
| 1        | 10 / 14 ( 71%) | 3.3V       |            |            |
| 2        | 6 / 8 ( 75%)   | 3.3V       |            |            |
+----------+----------------+------------+------------+------------+

Total Placer CPU time: 4 secs , REAL time: 4 secs 

Writing design to file dds_pro_impl_1_par.dir/5_1.udb ...


Start NBR router at 05:42:33 03/12/23

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in timing report. You should always run the timing    
      tool to verify your design.                                
*****************************************************************

Starting routing resource preassignment
Preassignment Summary:
--------------------------------------------------------------------------------
231 connections routed with dedicated routing resources
1 global clock signals routed
323 connections routed (of 1243 total) (25.99%)
---------------------------------------------------------
Clock routing summary:
Primary clocks (1 used out of 8 available):
#0  Signal &quot;clk_60M&quot;
       Clock   loads: 92    out of    92 routed (100.00%)
       Data    loads: 0     out of     1 routed (  0.00%)
Other clocks:
    Signal &quot;clk_12M_c&quot;
       Clock   loads: 0     out of     1 routed (  0.00%)
    Signal &quot;u_pll_60M.lscc_pll_inst.feedback_w&quot;
       Clock   loads: 1     out of     1 routed (100.00%)
---------------------------------------------------------
--------------------------------------------------------------------------------
Completed routing resource preassignment
WARNING - par: No master clock for
	generated clock	create_generated_clock -name {clk_60M} -source [get_pins {u_pll_60M/lscc_pll_inst/u_PLL_B/REFERENCECLK}] -multiply_by 5 [get_pins {u_pll_60M/lscc_pll_inst/u_PLL_B/OUTCORE }] .

Start NBR section for initial routing at 05:42:34 03/12/23
Level 4, iteration 1
11(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 2 secs 

Info: Initial congestion level at 75.00% usage is 0
Info: Initial congestion area  at 75.00% usage is 0 (0.00%)

Start NBR section for normal routing at 05:42:35 03/12/23
Level 4, iteration 1
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 2 secs 
Level 4, iteration 2
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 2 secs 
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 2 secs 

Start NBR section for post-routing at 05:42:35 03/12/23

End NBR router with 0 unrouted connection
WARNING - par: No master clock for
	generated clock	create_generated_clock -name {clk_60M} -source [get_pins {u_pll_60M/lscc_pll_inst/u_PLL_B/REFERENCECLK}] -multiply_by 5 [get_pins {u_pll_60M/lscc_pll_inst/u_PLL_B/OUTCORE }] .

Starting full timing analysis...


<A name="par_nbrsum"></A><B><U><big>NBR Summary</big></U></B>
-----------
  Number of unrouted connections : 0 (0.00%)
  Estimated worst slack&lt;setup&gt; : &lt;n/a&gt;
  Estimated worst slack&lt;hold &gt; : &lt;n/a&gt;
  Timing score&lt;setup&gt; : 0
  Timing score&lt;hold &gt; : 0
  Number of connections with timing violations&lt;setup&gt; : 0 (0.00%)
  Number of connections with timing violations&lt;hold &gt; : 0 (0.00%)
-----------


Total CPU time 1 secs 
Total REAL time: 2 secs 
Completely routed.
End of route.  1243 routed (100.00%); 0 unrouted.

Writing design to file dds_pro_impl_1_par.dir/5_1.udb ...


All signals are completely routed.


PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack&lt;setup/&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Worst  slack&lt;hold /&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Number of errors = 0

Total CPU  Time: 6 secs 
Total REAL Time: 7 secs 
Peak Memory Usage: 118.32 MB


par done!

Note: user must run &apos;timing&apos; for timing closure signoff.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2022 Lattice Semiconductor Corporation,  All rights reserved.



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</PRE></DIV>

<DIV id="toc" class="radiant"><span onmousemove="showTocList()">Contents</span>
<UL id="toc_list">
<LI><A href=#par_cts>Cost Table Summary</A></LI>
<LI><A href=#par_best>Best Par Run</A></LI>
<LI><A href=#par_dus>Device utilization summary</A></LI>
<LI><A href=#par_clk>Clock Report</A></LI>
<LI><A href=#par_nbrsum>NBR Summary</A></LI>
</UL>
</DIV>

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